1. D. Sarkar, A. T. Wassie and E. S. Boyden, “Mapping the Fundamental Building Blocks of the Brain,” Lindau Nobel Laureate Meeting, 2016. 

  2. D. Sarkar, A. T. Wassie, A. Payne, K. D. Piatkevich, D. Oran, J.­B.Chang and E. S. Boyden, “100­ fold linear expansion of biological samples for nanoscale imaging,” Society for Neuroscience, 2016. 

  3. S. G. Rodriques, A. H. Marblestone, J. Scholvin, J. Dapello, D. Sarkar, M. Mankin, R. Gao, L. Wood and E. S. Boyden, “Multiplexed neural recording along a single optical fiber via optical reflectometry,” Journal of Biomedical Optics, Vol. 21, No. 5, pp. 057003, 2016.

  4. W. Cao, J. Jiang, J. Kang, D. Sarkar, W. Liu, and K. Banerjee, “Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next-Generation Low-Power VLSI,” IEDM Tech. Digest, Washington DC, December 7-9, 2015, pp. 12.3.1-12.3.4.

  5. D. Sarkar, X. Xie, W. Liu, W. Cao, J. Kang, Y. Gong, S. Kraemer, P. M. Ajayan and K. Banerjee, “A subthermionic tunnel field-effect transistor with an atomically thin channel,” Nature, Vol. 526, No. 7571, pp. 91, 2015. (highlighted in Nature News and Views)

  6. W. Cao, J. Kang, D. Sarkar, W. Liu and K. Banerjee, "2D Semiconductor FETs- Projections and Design for Sub-10 nm VLSI," IEEE Transactions on Electron Devices, Special Issue to commemorate the 60th anniversary of the IEDM, Vol. 62, No. 11, pp. 3459, 2015.

  7. D. Sarkar, X. Xie, J. Kang, H. Zhang, W. Liu, J. Navarrete, M. Moskovits and K. Banerjee, “ Functionalization of Transition Metal Dichalcogenides with Metallic Nanoparticles: Implications for Doping and Gas-Sensing,” Nano Lett., Vol. 15, No. 5, pp. 2852, 2015.

  8. W. Cao, J. Kang, D. Sarkar, W. Liu and K. Banerjee, “Performance Evaluation and Design Considerations of 2D Semiconductor Based FETs for Sub-10 nm VLSI,” IEDM Tech. Digest, pp. 729, 2014.

  9. X. Li, J. Kang, X. Xie, W. Liu, D. Sarkar, J. Mao and K. Banerjee, “Graphene Inductors for High -Frequency Applications –   Design, Fabrication,  Characterization , and Study of Skin  Effect,” IEDM Tech. Digest, pp. 120, 2014.

  10. D. Sarkar, W. Liu, X. Xie, A. Anselmo, S. Mitragotri and K. Banerjee, “Molybdenum Disulphide Based Field Effect Transistors for Next-Generation Label-free Biosensors,” ACS Nano. Vol. 8, No. 4, pp. 3992, 2014.

  11. X. Xie, D. Sarkar, W. Liu, J. Kang, O. Marinov, M. J. Deen, and K. Banerjee, “Low-Frequency Noise in Bilayer MoS2 Transistor,” ACS Nano. Vol. 8, No. 6, pp. 5633, 2014.

  12. J. Kang, W. Liu, D. Sarkar, D. Jena and K. Banerjee, “A Computational Study of Metal-Contacts to Monolayer Transition-Metal Dichalcogenide Semiconductors,” Phys. Rev. X. Vol. 4, No. 3, pp. 031005, 2014.

  13. W. Cao, D. Sarkar, Y. Khatami, J. Kang and K. Banerjee, “Subthreshold-Swing Physics Of Tunnel Field-Effect Transistors,” AIP Advances. Vol. 4, pp. 067141, 2014.

  14. J. Kang, W. Cao, X. Xie, D. Sarkar, W. Liu and K. Banerjee,  “Graphene and beyond-graphene 2D crystals for next-generation green electronics.,” Proc. SPIE 9083, Micro- and Nanotechnology Sensors, Systems, and Applications VI, pp. 908305, 2014.

  15. W. Liu, S. Krämer, D. Sarkar, H. Li, P. M. Ajayan, and K. Banerjee, “Controllable and Rapid Synthesis of High-Quality and Large-Area Bernal Stacked Bilayer Graphene using Chemical Vapor Deposition” ACS Chemistry of Materials, Vol. 26, No. 2, pp. 907, 2014.

  16. J. Kang, D. Sarkar, Y. Khatami, and K. Banerjee, “Proposal for All-Graphene Monolithic Logic Circuits,”  Appl. Phys. Lett., Vol. 103, No. 8, pp. 083113, 2013.

  17. W. Liu, J. Kang, W. Cao, D. Sarkar, Y. Khatami, D. Jena and K. Banerjee, “High-Performance Few-Layer-MoS2 Field-Effect-Transistor with Record Low Contact-Resistance ” IEDM Tech. Digest, pp. 808, 2013.

  18. D. Sarkar and K. Banerjee, “Impact-Ionization Field-Effect-Transistor Based Biosensors for Ultra-Sensitive  Detection of Biomolecules,” Appl. Phys. Lett, Vol. 102, No. 20, pp. 203110, 2013.

  19. D. Sarkar, H. Gossner, W. Hansch and K. Banerjee, “Tunnel-Field-Effect-Transistor Based Gas-Sensor: Introducing Gas Detection with A Quantum-Mechanical Transducer,” Appl. Phys. Lett, Vol. 102, No. 14, pp. 023110, 2013.

  20. W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena and K. Banerjee, “Role of Metal Contacts in Designing High-Performance Monolayer n-Type WSe2 Field-Effect-Transistors,” Nano Letters, Vol. 13, no. 5, pp. 1983, 2013.

  21. D. Sarkar and K. Banerjee, “Proposal for Tunnel-Field-Effect-Transistor as Ultra-Sensitive and Label-Free Biosensor,” Appl. Phys. Lett. Vol. 100, No. 14, pp. 143108, 2012. (highlighted in Nature Nanotechnology)

  22. D. Sarkar and K. Banerjee, “ Fundamental Limitations of Conventional-FET Biosensors: Quantum-Mechanical-Tunneling to the Rescue,” Device Research  Conference Tech. Digest, 2012.

  23. J. Kang, D. Sarkar, W. Liu, D.Jena and K. Banerjee, “A Computational Study of Metal-Contacts to Beyond-Graphene 2D Semiconductor Materials, ” IEDM Tech. Digest, pp. 808, 2012.

  24. D. Sarkar and K. Banerjee, “Metallic-Nanoparticle Assisted Enhanced Band-To-Band Tunneling Current,” Appl. Phys. Lett., Vol. 99, No. 13, pp. 133116, 2011.

  25. X. Li,  Z. Chen,  N. Shen, D. Sarkar, N. Singh, K. Banerjee, Guo-Qiang Lo, Dim-Lee Kwong, “Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire,” IEEE Elec. Dev. Lett, Vol. 32, No. 11, pp. 1492, 2011.

  26. D. Sarkar, C. Xu, H. Li, and K. Banerjee, “High-Frequency Behavior of Graphene-Based Interconnects – Part I: Impedance Modeling,” IEEE Trans. Elec. Dev., Vol. 58, No. 3, pp. 843, 2011.

  27. D. Sarkar, C. Xu, H. Li, and K. Banerjee, “High-Frequency Behavior of Graphene-Based Interconnects – Part II: Impedance Analysis and Implications for Inductor Design,” IEEE Trans. Elec. Dev., Vol. 58, No. 3, pp. 853, 2011.

  28. D. Sarkar, M. Krall, and K. Banerjee, “Electron-hole Duality During Band-to-Band Tunneling Process in Graphene-Nanoribbon Tunnel-Field-Effect Transistors,” Appl. Phys. Lett., Vol. 97, No. 26, pp. 263109, 2010.

  29. D. Sarkar, N. Singh and K. Banerjee, “A Novel Enhanced Electric-Field Impact-Ionization MOS Transistor,” IEEE Elec. Dev. Lett., Vol. 31, No. 11, pp. 1175, 2010.

  30. D. Sarkar, S. Thijs, D. Linten, C. Russ, H. Gossner and K. Banerjee, “A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices,” IEDM Tech. Digest, pp. 808, 2010.

  31. D. Sarkar, C. Xu, H. Li, and K. Banerjee, “AC Conductance Modeling and Analysis of Graphene Nanoribbon Interconnects,” IEEE Intl. Interconnect Tech. Conf. (IITC), pp.1, 2010.

  32. K. Banerjee, H. Li, C. Xu, Y. Khatami, H.F. Dadgour, D. Sarkar, W. Liu, “Prospects of Carbon Nanomaterials For Next-Generation Green Electronics,” IEEE Conf. Nanotech. (IEEE-NANO), pp. 56, 2010.

  33. D. Sarkar, H. Gossner and K. Banerjee, “Experimental Investigation of ESD Performance for Strained Silicon Nano-Devices,” ESD Forum, pp. 36, 2009.

  34. D. Sarkar, D. Datta, and S. Dasgupta, “Modelling of Leakage Current Mechanisms in nanoscale DG  MOSFET and its application to low power SRAM design ” Jnl. Comp., Vol. 3, No. 2, pp. 37, 2008.

  35. D. Sarkar, “Spin Selection in Resonant Tunneling Diode using Dilute Magnetic Semiconductors," Workshop Recent Adv. Low Dimen. Struc. Dev. (WRA-LDSD), Nottingham, UK, 2008.

  36. D. Sarkar, Implementation Of A Spintronics Full Adder,European Conf. Phys. Magnetism, Poland, June 2008.

  37. D. Sarkar, “A Novel Technique for Reduction of Gate Leakage Current Using Double Gate SiGe/Si/SiGe Heterostructure n-Channel Mosfet,” Intl. Conf. Low Dimen. Struc. Dev., Columbia, 2007.

  38. D. Sarkar, S. Ganguly, D. Datta, A.A.P. Sarab and S. Dasgupta, “Modeling of Leakages in Nanoscale DG MOSFET to Implement Low Power SRAM: a Device/Circuit Co-Design,” IEEE Intl. Conf. VLSI Design, Bangalore, India, 2007.

  39. D. Datta, A. A. Sarab, S. Ganguly, D. Sarkar and S. Dasgupta, “A New Design Architecture of Novel Nanoscale Device to Reduce Leakage Currents,” IEEE Silicon Nanotech. Workshop, HI, USA, 2006.


Carbon Integrated Electronics, H. Li, Y. Khatami, D. Sarkar, J. Kang, C. Xu, W. Liu, and K. Banerjee, in Intelligent Integrated Systems: Technologies, Devices and Architectures. Ed: S. Deleonibus, WSPC-Pan Stanford (Singapore) Publishers, 2014.